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-- Company: 
-- Engineer: 
-- 
-- Create Date: 30.11.2023 12:54:06
-- Design Name: 
-- Module Name: BraunsMultiplier - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.std_logic_arith.All;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity BraunsMultiplier is
    Port ( A : in STD_LOGIC_VECTOR(7 DOWNTO 0);
           B : in STD_LOGIC_VECTOR(7 DOWNTO 0);
           P : out STD_LOGIC_VECTOR(15 DOWNTO 0));
end BraunsMultiplier;

architecture Behavioral of BraunsMultiplier is
signal A1B0 : std_logic;
signal A0B1 : std_logic;
signal A2B0 : std_logic;
signal A1B1 : std_logic;
signal A0B2 : std_logic;
signal A3B0 : std_logic;
signal A2B1 : std_logic;
signal A1B2 : std_logic;
signal A0B3 : std_logic;
signal A4B0 : std_logic;
signal A3B1 : std_logic;
signal A2B2 : std_logic;
signal A1B3 : std_logic;
signal A0B4 : std_logic;
signal A5B0 : std_logic;
signal A4B1 : std_logic;
signal A3B2 : std_logic;
signal A2B3 : std_logic;
signal A1B4 : std_logic;
signal A0B5 : std_logic;
signal A6B0 : std_logic;
signal A5B1 : std_logic;
signal A4B2 : std_logic;
signal A3B3 : std_logic;
signal A2B4 : std_logic;
signal A1B5 : std_logic;
signal A0B6 : std_logic;
signal A7B0 : std_logic;
signal A6B1 : std_logic;
signal A5B2 : std_logic;
signal A4B3 : std_logic;
signal A3B4 : std_logic;
signal A2B5 : std_logic;
signal A1B6 : std_logic;
signal A0B7 : std_logic;
signal A7B1 : std_logic;
signal A6B2 : std_logic;
signal A5B3 : std_logic;
signal A4B4 : std_logic;
signal A3B5 : std_logic;
signal A2B6 : std_logic;
signal A1B7 : std_logic;
signal A7B2 : std_logic;
signal A6B3 : std_logic;
signal A5B4 : std_logic;
signal A4B5 : std_logic;
signal A3B6 : std_logic;
signal A2B7 : std_logic;
signal A7B3 : std_logic;
signal A6B4 : std_logic;
signal A5B5 : std_logic;
signal A4B6 : std_logic;
signal A3B7 : std_logic;
signal A7B4 : std_logic;
signal A6B5 : std_logic;
signal A5B6 : std_logic;
signal A4B7 : std_logic;
signal A7B5 : std_logic;
signal A6B6 : std_logic;
signal A5B7 : std_logic;
signal A7B6 : std_logic;
signal A6B7 : std_logic;
signal A7B7 : std_logic;
signal Cout1,Cout2,Cout3,Cout4,Cout5,Cout6,Cout7,Cout8,Cout9,Cout10,Cout11,Cout12,Cout13,Cout14,Cout15,Cout16,Cout17,Cout18,Cout19,Cout20 : std_logic;
signal Cout21,Cout22,Cout23,Cout24,Cout25,Cout26,Cout27,Cout28,Cout29,Cout30,Cout31,Cout32,Cout33,Cout34,Cout35,Cout36,Cout37,Cout38,Cout39,Cout40 : std_logic;
signal Cout41,Cout42,Cout43,Cout44,Cout45,Cout46,Cout47,Cout48,Cout49,Cout50,Cout51,Cout52,Cout53,Cout54,Cout55,Cout56 : std_logic;
signal S2,S3,S4,S5,S6,S7,S8,S10,S11,S12,S13,S14,S15,S16,S18,S19,S20 : std_logic;
signal S21,S22,S23,S24,S26,S27,S28,S29,S30,S31,S32,S34,S35,S36,S37 : std_logic;
signal S38,S39,S40,S42,S43,S44,S45,S46,S47,S48 : std_logic;
    
component fulladder
port (A: in std_logic;
    B: in std_logic;
    Cin: in std_logic;
    S: out std_logic;
    Cout: out std_logic);
end component;
    
component halfadder
port (A: in std_logic;
    B: in std_logic;
    S: out std_logic;   
    Cout: out std_logic);
end component;
      
begin
A1B0 <= A(1) and B(0);
A0B1 <= A(0) and B(1);
A2B0 <= A(2) and B(0);
A1B1 <= A(1) and B(1);
A0B2 <= A(0) and B(2);
A3B0 <= A(3) and B(0);
A2B1 <= A(2) and B(1);
A1B2 <= A(1) and B(2);
A0B3 <= A(0) and B(3);
A4B0 <= A(4) and B(0);
A3B1 <= A(3) and B(1);
A2B2 <= A(2) and B(2);
A1B3 <= A(2) and B(3);
A0B4 <= A(0) and B(4);
A5B0 <= A(5) and B(0);
A4B1 <= A(4) and B(1);
A3B2 <= A(3) and B(2);
A2B3 <= A(2) and B(3);
A1B4 <= A(1) and B(4);
A0B5 <= A(0) and B(5);
A6B0 <= A(6) and B(0);
A5B1 <= A(5) and B(1);
A4B2 <= A(4) and B(2);
A3B3 <= A(3) and B(3);
A2B4 <= A(2) and B(4);
A1B5 <= A(1) and B(5);
A0B6 <= A(0) and B(6);
A7B0 <= A(7) and B(0);
A6B1 <= A(6) and B(1);
A5B2 <= A(5) and B(2);
A4B3 <= A(4) and B(3);
A3B4 <= A(3) and B(4);
A2B5 <= A(2) and B(5);
A1B6 <= A(1) and B(6);
A0B7 <= A(0) and B(7);
A7B1 <= A(7) and B(1);
A6B2 <= A(6) and B(2);
A5B3 <= A(5) and B(3);
A4B4 <= A(4) and B(4);
A3B5 <= A(3) and B(5);
A2B6 <= A(2) and B(6);
A1B7 <= A(1) and B(7);
A7B2 <= A(7) and B(2);
A6B3 <= A(6) and B(3);
A5B4 <= A(5) and B(4);
A4B5 <= A(4) and B(5);
A3B6 <= A(3) and B(6);
A2B7 <= A(2) and B(7);
A7B3 <= A(7) and B(3);
A6B4 <= A(6) and B(4);
A5B5 <= A(5) and B(5);
A4B6 <= A(4) and B(6);
A3B7 <= A(3) and B(7);
A7B4 <= A(7) and B(4);
A6B5 <= A(6) and B(5);
A5B6 <= A(5) and B(6);
A4B7 <= A(4) and B(7);
A7B5 <= A(7) and B(5);
A6B6 <= A(6) and B(6);
A5B7 <= A(5) and B(7);
A7B6 <= A(7) and B(6);
A6B7 <= A(6) and B(7);
A7B7 <= A(7) and B(7);

PO : P(0) <= A(0) and B(0);

P1 : halfadder port map (A1B0,A0B1,P(1),Cout1);

S2_1 : fulladder port map (A2B0,A1B1,Cout1,S2,Cout2);
P2 : halfadder port map (A0B2,S2,P(2),Cout9);

S3_1 : fulladder port map (A3B0,A2B1,Cout2,S3,Cout3); 
S10_1 : fulladder port map (A1B2,S3,Cout9,S10,Cout10);
P3 : halfadder port map (A0B3,S10,P(3),Cout17);


S4_1 : fulladder port map (A4B0,A3B1,Cout3,S4,Cout4); 
S11_1 : fulladder port map (A2B2,S4,Cout10,S11,Cout11); 
S18_1 : fulladder port map (A1B3,S11,Cout17,S18,Cout18); 
P4 : halfadder port map (A0B4,S18,P(4),Cout25);

S5_1 : fulladder port map (A5B0,A4B1,Cout4,S5,Cout5);
S12_1 : fulladder port map (A3B2,S5,Cout11,S12,Cout12);
S19_1 : fulladder port map (A2B3,S12,Cout18,S19,Cout19);
S26_1 : fulladder port map (A1B4,S19,Cout25,S26,Cout26);
P5 : halfadder port map (A0B5,S26,P(5),Cout33);

S6_1 : fulladder port map (A6B0,A5B1,Cout5,S6,Cout6);
S13_1 : fulladder port map (A4B2,S6,Cout12,S13,Cout13);
S20_1 : fulladder port map (A3B3,S13,Cout19,S20,Cout20);
S27_1 : fulladder port map (A2B4,S20,Cout26,S27,Cout27);
S34_1 : fulladder port map (A1B5,S27,Cout33,S34,Cout34);
P6 : halfadder port map (A0B6,S34,P(6),Cout41);

S7_1 : fulladder port map (A7B0,A6B1,Cout6,S7,Cout7);
S14_1 : fulladder port map (A5B2,S7,Cout13,S14,Cout14);
S21_1 : fulladder port map (A4B3,S14,Cout20,S21,Cout21);
S28_1 : fulladder port map (A3B4,S21,Cout27,S28,Cout28);
S35_1 : fulladder port map (A2B5,S28,Cout34,S35,Cout35);
S42_1 : fulladder port map (A1B6,S35,Cout41,S42,Cout42);
P7 : halfadder port map (A0B7,S42,P(7),Cout49);

S8_1 : halfadder port map (A7B1,Cout7,S8,Cout8);
S15_1 : fulladder port map (A6B2,S8,Cout14,S15,Cout15);
S22_1 : fulladder port map (A5B3,S15,Cout21,S22,Cout22);
S29_1 : fulladder port map (A4B4,S22,Cout28,S29,Cout29);
S36_1 : fulladder port map (A3B5,S29,Cout35,S36,Cout36);
S43_1 : fulladder port map (A2B6,S36,Cout42,S43,Cout43);
P8 : fulladder port map (A1B7,S43,Cout49,P(8),Cout50);


S16_1 : fulladder port map (A7B2,Cout8,Cout15,S16,Cout16);
S23_1 : fulladder port map (A6B3,S16,Cout22,S23,Cout23);
S30_1 : fulladder port map (A5B4,S23,Cout29,S30,Cout30);
S37_1 : fulladder port map (A4B5,S30,Cout36,S37,Cout37);
S44_1 : fulladder port map (A3B6,S37,Cout43,S44,Cout44);
P9 : fulladder port map (A2B7,S44,Cout50,P(9),Cout51);

S24_1 : fulladder port map (A7B3,Cout16,Cout23,S24,Cout24);
S31_1 : fulladder port map (A6B4,S24,Cout30,S31,Cout31);
S38_1 : fulladder port map (A5B5,S31,Cout37,S38,Cout38);
S45_1 : fulladder port map (A4B6,S38,Cout44,S45,Cout45);
P10 : fulladder port map (A3B7,S45,Cout51,P(10),Cout52);

S32_1 : fulladder port map (A7B4,Cout24,Cout31,S32,Cout32);
S39_1 : fulladder port map (A6B5,S32,Cout38,S39,Cout39);
S46_1 : fulladder port map (A5B6,S39,Cout45,S46,Cout46);
P11 : fulladder port map (A4B7,S46,Cout52,P(11),Cout53);

S40_1 : fulladder port map (A7B5,Cout32,Cout39,S40,Cout40);
S47_1 : fulladder port map (A6B6,S40,Cout46,S47,Cout47);
P12 : fulladder port map (A5B7,S47,Cout53,P(12),Cout54);

S48_1 : fulladder port map (A7B6,Cout40,Cout47,S48,Cout48);
P13 : fulladder port map (A6B7,S48,Cout54,P(13),Cout55);

P14 : fulladder port map (A7B7,Cout48,Cout55,P(14),Cout56);

P15 : P(15) <= Cout56;


end Behavioral;