----Full Adder for 4X4 Brauns Multiplier
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity full_adder is
 Port ( A : in STD_LOGIC;
 B : in STD_LOGIC;
 Cin : in STD_LOGIC;
 S : out STD_LOGIC;
 Cout : out STD_LOGIC);
end full_adder;
 
architecture gate_level of full_adder is
begin
 S <= A XOR B XOR Cin ;
 Cout <= (A AND B) OR (Cin AND A) OR (Cin AND B) ;
end gate_level;
 -------------------------------------------------------------------------
----Half Adder for 4X4 Brauns Multiplier
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity half_adder is
Port ( A : in STD_LOGIC;
 B : in STD_LOGIC;
 S : out STD_LOGIC;
 Cout : out STD_LOGIC);
end half_adder;
 
architecture gate_level of half_adder is
 
begin
S <= A XOR B  ;
 Cout <= (A AND B) ;
end gate_level;
------------------------------------------------------------------------- 
---VHDL Code for 4X4 Brauns Multiplier
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity brauns_multipler is
Port ( A : in  STD_LOGIC_VECTOR (3 downto 0);
B : in  STD_LOGIC_VECTOR (3 downto 0);
       P : out  STD_LOGIC_VECTOR (7 downto 0));
end brauns_multipler;
 
architecture Behavioural of brauns_multipler is
 
signal A1B0 : std_logic;
signal A0B1 : std_logic;
signal A2B0 : std_logic;
signal A1B1 : std_logic;
signal A0B2 : std_logic;
signal A3B0 : std_logic;
signal A2B1 : std_logic;
signal A1B2 : std_logic;
signal A0B3 : std_logic;
signal A3B1 : std_logic;
signal A2B2 : std_logic;
signal A1B3 : std_logic;
signal A3B2 : std_logic;
signal A2B3 : std_logic;
signal A3B3 : std_logic;
 
signal C1 : std_logic;---P2
signal P2_1 : std_logic;
 
signal C2_1 : std_logic;---P3
signal P3_1 : std_logic;
signal C2 : std_logic;
signal P3_2 : std_logic;
 
signal C3_1 : std_logic;----P4
signal P4_1 : std_logic;
signal C3_2 : std_logic;
signal P4_2 : std_logic;
signal C3   : std_logic;
 
signal C4_1 : std_logic;-----P5
signal C4_2 : std_logic;
signal P5_1 : std_logic;
signal C4   : std_logic;
 
signal C5_1 : std_logic;----P6
signal C5 : std_logic;
 
signal C6 : std_logic;
 
component full_adder
port (A : in STD_LOGIC;
 B : in STD_LOGIC;
 Cin : in STD_LOGIC;
 S : out STD_LOGIC;
 Cout : out STD_LOGIC);
end component;
 
component half_adder
port (A : in STD_LOGIC;
 B : in STD_LOGIC;
  S : out STD_LOGIC;
 Cout : out STD_LOGIC);
end component;
 
begin
A1B0 <= A(1) and B(0) ;
A0B1 <= A(0) and B(1) ;
A2B0 <= A(2) and B(0) ;
A1B1 <= A(1) and B(1) ;
A0B2 <= A(0) and B(2) ;
A3B0 <= A(3) and B(0) ;
A2B1 <= A(2) and B(1) ;
A1B2 <= A(1) and B(2) ;
A0B3 <= A(0) and B(3) ;
A3B1 <= A(3) and B(1) ;
A2B2 <= A(2) and B(2) ;
A1B3 <= A(1) and B(3) ;
A3B2 <= A(3) and B(2) ;
A2B3 <= A(2) and B(3) ;
A3B3 <= A(3) and B(3) ;
 
P0 : P(0) <= A(0) and B(0) ;
 
P1_0 : half_adder port map (A=>A1B0 , B=>A0B1 ,S=> P(1), Cout=>C1);
 
P21 : full_adder port map (A=>A2B0 , B=>A1B1 , Cin=>C1, S=>P2_1, Cout=>C2_1);
P2_0 : half_adder port map (A=>A0B2 , B=>P2_1 , S=>P(2), Cout=>C2);
 
P31 : full_adder port map (A=>A3B0 , B=>A2B1, Cin=>C2_1, S=>P3_1,Cout=>C3_1);
P32 : full_adder port map (A=>A1B2, B=>P3_1 ,Cin=>C2, S=>P3_2,Cout=>C3_2);
P3_0 : half_adder port map (A=>A0B3, B=>P3_2, S=>P(3),Cout=>C3);
 
P41 : half_adder port map (A=>A3B1 , B=>C3_1,S=>P4_1,Cout=>C4_1);
P42 : full_adder port map (A=>A2B2 , B=>P4_1, Cin=>C3_2, S=>P4_2,Cout=>C4_2);
P4_0 : full_adder port map (A=>A1B3 , B=>P4_2, Cin=>C3, S=>P(4),Cout=>C4);
 
P51 : full_adder port map (A=>A3B2 , B=>C4_1, Cin=>C4_2, S=>P5_1,Cout=>C5_1);
P5_0   : full_adder port map (A=>A2B3 , B=>P5_1, Cin=>C4, S=>P(5),Cout=>C5);
 
P6 : full_adder port map (A=>A3B3 , B=>C5_1, Cin=>C5, S=>P(6), Cout=> C6);
P7  : P(7) <= C6;
end Behavioural;