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-- Company: 
-- Engineer: 
-- 
-- Create Date: 07.12.2023 09:43:51
-- Design Name: 
-- Module Name: Wallace - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Wallace is
Port ( A : in std_logic_vector (7 downto 0);
       B : in std_logic_vector (7 downto 0);
       P : out std_logic_vector (15 downto 0));
end Wallace;

architecture Behavioral of Wallace is

component Fulladder is
Port ( A : in std_logic;
       B : in std_logic;
       Cin : in std_logic;
       Sum : out std_logic;
       Cout : out std_logic);
end component;

Component halfadder is
Port ( A : in std_logic;
       B : in std_logic;
       Sum : out std_logic;
       Cout : out std_logic);    
end component; 

Signal S2,S3,S4,S5,S6,S7,S8,S10,S11,S12,S13,S14,S15,S16,S18,S19,S20,S21,S22,S23,S24,S26,S27,S28,S29,S30,S31,S32,S34,S35,S36,S37,S38,S39,S40,S42,S43,S44,S45,S46,S47,S48 : std_logic;
Signal C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11,C12,C13,C14,C15,C16,C17,C18,C19,C20,C21,C22,C23,C24,C25,C26,C27,C28,C29,C30,C31,C32,C33,C34,C35,C36,C37,C38,C39,C40,C41,C42,C43,C44,C45,C46,C47,C48,C49,C50,C51,C52,C53,C54,C55 : std_logic;

signal A1B0 : std_logic;
Signal A2B0 : std_logic;
Signal A3B0 : std_logic;
Signal A4B0 : std_logic;
Signal A5B0 : std_logic;
Signal A6B0 : std_logic;
Signal A7B0 : std_logic;

Signal A0B1 : std_logic;
Signal A1B1 : std_logic;
Signal A2B1 : std_logic;
Signal A3B1 : std_logic;
Signal A4B1 : std_logic;
Signal A5B1 : std_logic;
Signal A6B1 : std_logic;
Signal A7B1 : std_logic;

Signal A0B2 : std_logic;
Signal A1B2 : std_logic;
Signal A2B2 : std_logic;
Signal A3B2 : std_logic;
Signal A4B2 : std_logic;
Signal A5B2 : std_logic;
Signal A6B2 : std_logic;
Signal A7B2 : std_logic;

Signal A0B3 : std_logic;
Signal A1B3 : std_logic;
Signal A2B3 : std_logic;
Signal A3B3 : std_logic;
Signal A4B3 : std_logic;
Signal A5B3 : std_logic;
Signal A6B3 : std_logic;
Signal A7B3 : std_logic;

Signal A0B4 : std_logic;
Signal A1B4 : std_logic;
Signal A2B4 : std_logic;
Signal A3B4 : std_logic;
Signal A4B4 : std_logic;
Signal A5B4 : std_logic;
Signal A6B4 : std_logic;
Signal A7B4 : std_logic;

Signal A0B5 : std_logic;
Signal A1B5 : std_logic;
Signal A2B5 : std_logic;
Signal A3B5 : std_logic;
Signal A4B5 : std_logic;
Signal A5B5 : std_logic;
Signal A6B5 : std_logic;
Signal A7B5 : std_logic;

Signal A0B6 : std_logic;
Signal A1B6 : std_logic;
Signal A2B6 : std_logic;
Signal A3B6 : std_logic;
Signal A4B6 : std_logic;
Signal A5B6 : std_logic;
Signal A6B6 : std_logic;
Signal A7B6 : std_logic;

Signal A0B7 : std_logic;
Signal A1B7 : std_logic;
Signal A2B7 : std_logic;
Signal A3B7 : std_logic;
Signal A4B7 : std_logic;
Signal A5B7 : std_logic;
Signal A6B7 : std_logic;
Signal A7B7 : std_logic;


begin

A1B0 <= A(1) and B(0);
A2B0 <= A(2) and B(0);
A3B0 <= A(3) and B(0);
A4B0 <= A(4) and B(0);
A5B0 <= A(5) and B(0);
A6B0 <= A(6) and B(0);
A7B0 <= A(7) and B(0);

A0B1 <= A(0) and B(1);
A1B1 <= A(1) and B(1);
A2B1 <= A(2) and B(1);
A3B1 <= A(3) and B(1);
A4B1 <= A(4) and B(1);
A5B1 <= A(5) and B(1);
A6B1 <= A(6) and B(1);
A7B1 <= A(7) and B(1);

A0B2 <= A(0) and B(2);
A1B2 <= A(1) and B(2);
A2B2 <= A(2) and B(2);
A3B2 <= A(3) and B(2);
A4B2 <= A(4) and B(2);
A5B2 <= A(5) and B(2);
A6B2 <= A(6) and B(2);
A7B2 <= A(7) and B(2);

A0B3 <= A(0) and B(3);
A1B3 <= A(1) and B(3);
A2B3 <= A(2) and B(3);
A3B3 <= A(3) and B(3);
A4B3 <= A(4) and B(3);
A5B3 <= A(5) and B(3);
A6B3 <= A(6) and B(3);
A7B3 <= A(7) and B(3);

A0B4 <= A(0) and B(4);
A1B4 <= A(1) and B(4);
A2B4 <= A(2) and B(4);
A3B4 <= A(3) and B(4);
A4B4 <= A(4) and B(4);
A5B4 <= A(5) and B(4);
A6B4 <= A(6) and B(4);
A7B4 <= A(7) and B(4);

A0B5 <= A(0) and B(5);
A1B5 <= A(1) and B(5);
A2B5 <= A(2) and B(5);
A3B5 <= A(3) and B(5);
A4B5 <= A(4) and B(5);
A5B5 <= A(5) and B(5);
A6B5 <= A(6) and B(5);
A7B5 <= A(7) and B(5);

A0B6 <= A(0) and B(6);
A1B6 <= A(1) and B(6);
A2B6 <= A(2) and B(6);
A3B6 <= A(3) and B(6);
A4B6 <= A(4) and B(6);
A5B6 <= A(5) and B(6);
A6B6 <= A(6) and B(6);
A7B6 <= A(7) and B(6);

A0B7 <= A(0) and B(7);
A1B7 <= A(1) and B(7);
A2B7 <= A(2) and B(7);
A3B7 <= A(3) and B(7);
A4B7 <= A(4) and B(7);
A5B7 <= A(5) and B(7);
A6B7 <= A(6) and B(7);
A7B7 <= A(7) and B(7);

-- Stage 1
P0 : P(0) <= A (0) and B (0) ;

ha11 : Halfadder Port map ( A=>A1B0, B=>A0B1, Sum=>P(1), Cout=>C1);
fa12 : Fulladder Port map ( A=>A2B0, B=>A1B1, Cin=>A2B0, Sum=>S2, Cout=>C2);
fa13 : Fulladder Port map ( A=>A3B0, B=>A2B1, Cin=>A1B2, Sum=>S3, Cout=>C3);
fal4 : Fulladder Port map ( A=>A4B0, B=>A3B1, Cin=>A2B2, Sum=>S4, Cout=>C4);
fal5 : Fulladder Port map ( A=>A5B0, B=>A4B1, Cin=>A3B2, Sum=>S5, Cout=>C5);
fal6 : Fulladder Port map ( A=>A6B0, B=>A5B1, Cin=>A4B2, Sum=>S6, Cout=>C6);
fal7 : Fulladder Port map ( A=>A7B0, B=>A6B1, Cin=>A5B2, Sum=>S7, Cout=>C7);
ha18 : Halfadder Port map ( A=>A7B1, B=>A6B2, Sum=>S8, Cout=>C8);

-- Stage 2
ha21 : Halfadder Port map ( A=>S2, B=>C1, Sum=>P(2), Cout=>C9);
fa22 : Fulladder Port map ( A=>A0B3, B=>S3, Cin=>C2, Sum=>S10, Cout=>C10);
fa23 : Fulladder Port map ( A=>A1B3, B=>S4, Cin=>C3, Sum=>S11, Cout=>C11);
fa24 : Fulladder Port map ( A=>A2B3, B=>S5, Cin=>C4, Sum=>S12, Cout=>C12);
fa25 : Fulladder Port map ( A=>A3B3, B=>S6, Cin=>C5, Sum=>S13, Cout=>C13);
fa26 : Fulladder Port map ( A=>A4B3, B=>S7, Cin=>C6, Sum=>S14, Cout=>C14);
fa27 : Fulladder Port map ( A=>A5B3, B=>S8, Cin=>C7, Sum=>S15, Cout=>C15);
fa28 : Fulladder Port map ( A=>A7B2, B=>A6B3, Cin=>C8, Sum=>S16, Cout=>C16);


-- Stage 3
ha31 : Halfadder Port map ( A=>S10, B=>C9, Sum=>P(3), Cout=>C17);
fa32 : Fulladder Port map ( A=>A0B4, B=>S11, Cin=>C10, Sum=>S18, Cout=>C18);
fa33 : Fulladder Port map ( A=>A1B4, B=>S12, Cin=>C11, Sum=>S19, Cout=>C19);
fa34 : Fulladder Port map ( A=>A2B4, B=>S13, Cin=>C12, Sum=>S20, Cout=>C20);
fa35 : Fulladder Port map ( A=>A3B4, B=>S14, Cin=>C13, Sum=>S21, Cout=>C21);
fa36 : Fulladder Port map ( A=>A4B4, B=>S15, Cin=>C14, Sum=>S22, Cout=>C22);
fa37 : Fulladder Port map ( A=>A5B4, B=>S16, Cin=>C15, Sum=>S23, Cout=>C23);
fa38 : Fulladder Port map ( A=>A7B3, B=>A6B4, Cin=>C16, Sum=>S24, Cout=>C24);

--Stage 4
ha41 : Halfadder Port map ( A=>S18, B=>C17, Sum=>P(4), Cout=>C25);
fa42 : Fulladder Port map ( A=>A0B5, B=>S19, Cin=>C18, Sum=>S26, Cout=>C26);
fa43 : Fulladder Port map ( A=>A1B5, B=>S20, Cin=>C19, Sum=>S27, Cout=>C27);
fa44 : Fulladder Port map ( A=>A2B5, B=>S21, Cin=>C20, Sum=>S28, Cout=>C28);
fa45 : Fulladder Port map ( A=>A3B5, B=>S22, Cin=>C21, Sum=>S29, Cout=>C29);
fa46 : Fulladder Port map ( A=>A4B5, B=>S23, Cin=>C22, Sum=>S30, Cout=>C30);
fa47 : Fulladder Port map ( A=>A5B5, B=>S24, Cin=>C23, Sum=>S31, Cout=>C31);
fa48 : Fulladder Port map ( A=>A7B4, B=>A6B5, Cin=>C24, Sum=>S32, Cout=>C32);

--Stage 5
ha51 : Halfadder Port map ( A=>S26, B=>C25, Sum=>P(5), Cout=>C33);
fa52 : Fulladder Port map ( A=>A0B6, B=>S27, Cin=>C26, Sum=>S34, Cout=>C34);
fa53 : Fulladder Port map ( A=>A1B6, B=>S28, Cin=>C27, Sum=>S35, Cout=>C35);
fa54 : Fulladder Port map ( A=>A2B6, B=>S29, Cin=>C28, Sum=>S36, Cout=>C36);
fa55 : Fulladder Port map ( A=>A3B6, B=>S30, Cin=>C29, Sum=>S37, Cout=>C37);
fa56 : Fulladder Port map ( A=>A4B6, B=>S31, Cin=>C30, Sum=>S38, Cout=>C38);
fa57 : Fulladder Port map ( A=>A5B6, B=>S32, Cin=>C31, Sum=>S39, Cout=>C39);
fa58 : Fulladder Port map ( A=>A7B5, B=>A6B6, Cin=>C32, Sum=>S40, Cout=>C40);

--Stage 6
ha61 : Halfadder Port map ( A=>S34, B=>C33, Sum=>P(6), Cout=>C41);
fa62 : Fulladder Port map ( A=>A0B7, B=>S35, Cin=>C34, Sum=>S42, Cout=>C43);
fa63 : Fulladder Port map ( A=>A1B7, B=>S36, Cin=>C35, Sum=>S43, Cout=>C45);
fa64 : Fulladder Port map ( A=>A2B7 ,B=>S37, Cin=>C36, Sum=>S44, Cout=>C47);
fa65 : Fulladder Port map ( A=>A3B7, B=>S38, Cin=>C37, Sum=>S45, Cout=>C49);
fa66 : Fulladder Port map ( A=>A4B7, B=>S39, Cin=>C38, Sum=>S46, Cout=>C51);
fa67 : Fulladder Port map ( A=>A5B7, B=>S40, Cin=>C39, Sum=>S47, Cout=>C53);
fa68 : Fulladder Port map ( A=>A7B6, B=>A6B7, Cin=>C40, Sum=>S48, Cout=>C55);

--Stage 7
ha71 : Halfadder Port map ( A=>S42, B=>C41, Sum=>P(7), Cout=>C42);
fa72 : Fulladder Port map ( A=>S43, B=>C43, Cin=>C42, Sum=>P(8), Cout=>C44);
fa73 : Fulladder Port map ( A=>S44, B=>C45, Cin=>C44, Sum=>P(9), Cout=>C46);
fa74 : Fulladder Port map ( A=>S45, B=>C47, Cin=>C46, Sum=>P(10), Cout=>C48);
fa75 : Fulladder Port map ( A=>S46, B=>C49, Cin=>C48, Sum=>P(11), Cout=>C50);
fa76 : Fulladder Port map ( A=>S47, B=>C51, Cin=>C50, Sum=>P(12), Cout=>C52);
fa77 : Fulladder Port map ( A=>S48, B=>C53, Cin=>C52, Sum=>P(13), Cout=>C54);
fa78 : Fulladder Port map ( A=>A7B7, B=>C55, Cin=>C54, Sum=>P(14), Cout=>P(15));

end Behavioral;