library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;  -- Needed for integer operations

entity ClockDivider is
    Port (
        clk_in    : in  STD_LOGIC;   
        slow_clk  : out STD_LOGIC;   
        clk_test  : out STD_LOGIC    
    );
end ClockDivider;

architecture Behavioral of ClockDivider is
    -- Integer counter to count clock cycles
    signal counter : integer := 0;

    -- Toggle signal that flips after the counter reaches max
    signal toggle  : STD_LOGIC := '0';
begin
--- triggered on the rising edge of the input clock
    process(clk_in)
    begin
        if rising_edge(clk_in) then
            --freq is 100 M HZ , so the T is 1/100000000 = 10 ns
            -- for 5 sec, no of counts requrired : 5sec/10 ns = 500000000
           
           
            if counter = 500000000 then
                counter <= 0;             -- Reset the counter
                toggle  <= not toggle;    -- Flip the toggle signal 
            else
                counter <= counter + 1;   -- Keep counting clock cycles
            end if;
        end if;
    end process;


    slow_clk <= toggle;
    clk_test <= toggle;

end Behavioral;

----------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Top is
    Port (
        clk    : in  STD_LOGIC;    -- Onboard 100MHz clock
        btnC   : in  STD_LOGIC;    -- Reset button
        SW0    : in  STD_LOGIC;    -- Input bit
        LED0   : out STD_LOGIC;    -- FSM Output Z
        LED1   : out STD_LOGIC     -- Clock debug LED
    );
end Top;

architecture Structural of Top is
    signal slow_clk : STD_LOGIC;
    signal clk_test : STD_LOGIC;
begin
    -- Clock Divider instantiation
    clkdiv_inst : entity work.ClockDivider
        port map (
            clk_in   => clk,
            slow_clk => slow_clk,
            clk_test => clk_test
        );

    --  FSM instance instantiation for 1100
    fsm_inst : entity work.fsm_1100
        port map (
            clk   => slow_clk,
            reset => btnC,
            X     => SW0,
            Z     => LED0
        );

    -- LED1 at R2  sync with internal clk  
    LED1 <= clk_test;

end Structural;
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity fsm_1100 is
    Port (
        clk   : in  STD_LOGIC;
        reset : in  STD_LOGIC;
        X     : in  STD_LOGIC;
        Z     : out STD_LOGIC
    );
end fsm_1100;

architecture Behavioral of fsm_1100 is
       signal Q1, Q0 : STD_LOGIC := '0';
        signal D1, D0 : STD_LOGIC;
begin

    -- States using D flip-flops
    process(clk, reset)
    begin
        if reset = '1' then
            Q1 <= '0';
            Q0 <= '0';
	    Z <= '0';

        elsif rising_edge(clk) 
          then
            Q1 <= D1;
            Q0 <= D0;
            -- Sync Output logic inside clocked process
            Z <= Q1 and Q0 and (not X); 
        end if;
    end process;

    D1 <= (Q0 and X) or (Q1 and not Q0);
    D0 <= (not Q1 and not Q0 and X) or (Q1 and not Q0 and not X);

end Behavioral;
------------------------------------------------------------------------------------------------
set_property PACKAGE_PIN W5 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]


set_property PACKAGE_PIN T17 [get_ports btnC]
set_property IOSTANDARD LVCMOS33 [get_ports btnC]


set_property PACKAGE_PIN V17 [get_ports SW0]
set_property IOSTANDARD LVCMOS33 [get_ports SW0]


set_property PACKAGE_PIN L1 [get_ports LED0]
set_property IOSTANDARD LVCMOS33 [get_ports LED0]


set_property PACKAGE_PIN P1 [get_ports LED1]
set_property IOSTANDARD LVCMOS33 [get_ports LED1]