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-- Company: 
-- Engineer: 
-- 
-- Create Date: 09.12.2023 13:30:32
-- Design Name: 
-- Module Name: Wallace - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Wallace is
Port ( A : in STD_LOGIC_VECTOR (7 downto 0) ;
B : in STD_LOGIC_VECTOR (7 downto 0) ;
P : out STD_LOGIC_VECTOR (15 downto 0)) ;
end Wallace;

architecture Behavioural of Wallace is

component Fulladder
port (A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
Sum : out STD_LOGIC;
Cout : out STD_LOGIC) ;
end component;

component Halfadder 
port (A : in STD_LOGIC;
B : in STD_LOGIC;
Sum : out STD_LOGIC;
Cout : out STD_LOGIC) ; 
end component;
-------------------------------------------------- Wallace Tree Multiplier Architecture



signal S2, S3, S4, S5, S6, S7 : std_logic;
signal S9, S10, S11, S12, S13, S14 : std_logic;
signal S16, S17, S18, S19, S20, S21 : std_logic;
signal S23, S24, S25, S26, S27, S28 : std_logic;
signal S30, S31, S32, S33, S34, S35 : std_logic;
signal S37, S38, S39, S40, S41, S42 : std_logic;
signal S44, S45, S46, S47, S48, S49 : std_logic;


signal C1, C2, C3, C4, C5, C6, C7 : std_logic;
signal C8, C9, C10, C11, C12, C13, C14  : std_logic;
signal C15, C16, C17, C18, C19, C20, C21 : std_logic;
signal C22, C23, C24, C25, C26, C27, C28 : std_logic;
signal C29, C30, C31, C32, C33, C34, C35 : std_logic;
signal C36, C37, C38, C39, C40, C41, C42 : std_logic;
signal C43, C44, C45, C46, C47, C48, C49 : std_logic;
signal C50, C51, C52, C53, C54, C55 : std_logic;


signal A1B0, A2B0, A3B0, A4B0, A5B0, A6B0, A7B0 : std_logic;
signal A0B1, A1B1, A2B1, A3B1, A4B1, A5B1, A6B1, A7B1 : std_logic;
signal A0B2, A1B2, A2B2, A3B2, A4B2, A5B2, A6B2, A7B2 : std_logic;
signal A0B3, A1B3, A2B3, A3B3, A4B3, A5B3, A6B3, A7B3 : std_logic;
signal A0B4, A1B4, A2B4, A3B4, A4B4, A5B4, A6B4, A7B4 : std_logic;
signal A0B5, A1B5, A2B5, A3B5, A4B5, A5B5, A6B5, A7B5 : std_logic;
signal A0B6, A1B6, A2B6, A3B6, A4B6, A5B6, A6B6, A7B6 : std_logic;
signal A0B7, A1B7, A2B7, A3B7, A4B7, A5B7, A6B7, A7B7 : std_logic;

begin

A1B0 <= A (1) and B (0) ;
A2B0 <= A (2) and B (0) ;
A3B0 <= A (3) and B (0) ;
A4B0 <= A (4) and B (0) ;
A5B0 <= A (5) and B (0) ;
A6B0 <= A (6) and B (0) ;
A7B0 <= A (7) and B (0) ;

A0B1 <= A (0) and B (1) ;
A1B1 <= A (1) and B (1) ;
A2B1 <= A (2) and B (1) ;
A3B1 <= A (3) and B (1) ;
A4B1 <= A (4) and B (1) ;
A5B1 <= A (5) and B (1) ;
A6B1 <= A (6) and B (1) ;
A7B1 <= A (7) and B (1) ;

A0B2 <= A (0) and B (2) ;
A1B2 <= A (1) and B (2) ;
A2B2 <= A (2) and B (2) ;
A3B2 <= A (3) and B (2) ;
A4B2 <= A (4) and B (2) ;
A5B2 <= A (5) and B (2) ;
A6B2 <= A (6) and B (2) ;
A7B2 <= A (7) and B (2) ;

A0B3 <= A (0) and B (3) ;
A1B3 <= A (1) and B (3) ;
A2B3 <= A (2) and B (3) ;
A3B3 <= A (3) and B (3) ;
A4B3 <= A (4) and B (3) ;
A5B3 <= A (5) and B (3) ;
A6B3 <= A (6) and B (3) ;
A7B3 <= A (7) and B (3) ;

A0B4 <= A (0) and B (4) ;
A1B4 <= A (1) and B (4) ;
A2B4 <= A (2) and B (4) ;
A3B4 <= A (3) and B (4) ;
A4B4 <= A (4) and B (4) ;
A5B4 <= A (5) and B (4) ;
A6B4 <= A (6) and B (4) ;
A7B4 <= A (7) and B (4) ;

A0B5 <= A (0) and B (5) ;
A1B5 <= A (1) and B (5) ;
A2B5 <= A (2) and B (5) ;
A3B5 <= A (3) and B (5) ;
A4B5 <= A (4) and B (5) ;
A5B5 <= A (5) and B (5) ;
A6B5 <= A (6) and B (5) ;
A7B5 <= A (7) and B (5) ;
 
A0B6 <= A (0) and B (6) ;
A1B6 <= A (1) and B (6) ;
A2B6 <= A (2) and B (6) ;
A3B6 <= A (3) and B (6) ;
A4B6 <= A (4) and B (6) ;
A5B6 <= A (5) and B (6) ;
A6B6 <= A (6) and B (6) ;
A7B6 <= A (7) and B (6) ;

A0B7 <= A (0) and B (7) ;
A1B7 <= A (1) and B (7) ;
A2B7 <= A (2) and B (7) ;
A3B7 <= A (3) and B (7) ;
A4B7 <= A (4) and B (7) ;
A5B7 <= A (5) and B (7) ;
A6B7 <= A (6) and B (7) ;
A7B7 <= A (7) and B (7) ;



PO : P(0) <= A (0) and B(0);

hall: Halfadder port map (A1B0, A0B1, P(1), C1) ;
fa12: Fulladder port map (A2B0, A1B1, A0B2, S2, C2) ;
fa13: Fulladder port map (A2B1, A1B2, A0B3, S3, C3) ;
fa14: Fulladder port map (A2B2, A1B3, A0B4, S4, C4) ;
fa15: Fulladder port map (A2B3, A1B4, A0B5, S5, C5) ;
fa16: Fulladder port map (A2B4, A1B5, A0B6, S6, C6) ;
fa17: Fulladder port map (A2B5, A1B6, A0B7, S7, C7) ;


ha21: Halfadder port map (S2, C1, P(2), C8) ;
fa22: Fulladder port map (A3B0, S3, C2, S9, C9) ;
fa23: Fulladder port map (A3B1, S4, C3, S10, C10) ;
fa24: Fulladder port map (A3B2, S5, C4, S11, C11) ;
fa25: Fulladder port map (A3B3, S6, C5, S12, C12) ;
fa26: Fulladder port map (A3B4, S7, C6, S13, C13) ;
fa27: Fulladder port map (A2B6, A1B7, C7, S14, C14) ;


ha31: Halfadder port map (S9, C8, P(3), C15) ;
fa32: Fulladder port map (A4B0, S10, C9, S16, C16) ;
fa33: Fulladder port map (A4B1, S11, C10, S17, C17) ;
fa34: Fulladder port map (A4B2, S12, C11, S18, C18) ;
fa35: Fulladder port map (A4B3, S13, C12, S19, C19) ;
fa36: Fulladder port map (A3B5, S14, C13, S20, C20) ;
fa37: Fulladder port map (A3B6, A2B7, C14, S21, C21) ; 


ha41: Halfadder port map (S16, C15, P(4), C22) ;
fa42: Fulladder port map (A5B0, S17, C16, S23, C23) ;
fa43: Fulladder port map (A5B1, S18, C17, S24, C24) ;
fa44: Fulladder port map (A5B2, S19, C18, S25, C25) ;
fa45: Fulladder port map (A4B4, S20, C19, S26, C26) ;
fa46: Fulladder port map (A4B5, S21, C20, S27, C27) ;
fa47: Fulladder port map (A4B6, A3B7, C21, S28, C28) ; 


ha51: Halfadder port map (S23, C22, P(5), C29) ;
fa52: Fulladder port map (A6B0, S24, C23, S30, C30) ;
fa53: Fulladder port map (A6B1, S25, C24, S31, C31) ;
fa54: Fulladder port map (A5B3, S26, C25, S32, C32) ;
fa55: Fulladder port map (A5B4, S27, C26, S33, C33) ;
fa56: Fulladder port map (A5B5, S28, C27, S34, C34) ;
fa57: Fulladder port map (A5B6, A4B7, C28, S35, C35) ; 


ha61: Halfadder port map (S30, C29, P(6), C36) ;
fa62: Fulladder port map (A7B0, S31, C30, S37, C37) ;
fa63: Fulladder port map (A6B2, S32, C31, S38, C38) ;
fa64: Fulladder port map (A6B3, S33, C32, S39, C39) ;
fa65: Fulladder port map (A6B4, S34, C33, S40, C40) ;
fa66: Fulladder port map (A6B5, S35, C34, S41, C41) ;
fa67: Fulladder port map (A6B6, A5B7, C35, S42, C42) ; 


ha71: Halfadder port map (S37, C36, P(7), C43) ;
fa72: Fulladder port map (A7B1, S38, C37, S44, C44) ;
fa73: Fulladder port map (A7B2, S39, C38, S45, C45) ;
fa74: Fulladder port map (A7B3, S40, C39, S46, C46) ;
fa75: Fulladder port map (A7B4, S41, C40, S47, C47) ;
fa76: Fulladder port map (A7B5, S42, C41, S48, C48) ;
fa77: Fulladder port map (A7B6, A6B7, C42, S49, C49) ; 


ha81: Halfadder port map (S44, C43, P(8), C50) ;
fa82: Fulladder port map (S45, C44, C50, P(9),C51) ;
fa83: Fulladder port map (S46, C45, C51, P(10), C52) ;
fa84: Fulladder port map (S47, C46, C52, P(11), C53) ;
fa85: Fulladder port map (S48, C47, C53, P(12), C54) ;
fa86: Fulladder port map (S49, C48, C54, P(13), C55) ;
fa87: Fulladder port map (A7B7, C49, C55, P(14), P(15)) ; 


end Behavioural;