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-- Company: 
-- Engineer: 
-- 
-- Create Date: 07.12.2023 11:53:41
-- Design Name: 
-- Module Name: Wallace2 - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Wallace2 is
    Port ( A : in std_logic_vector (7 downto 0);
           B : in std_logic_vector (7 downto 0);
           P : out std_logic_vector (15 downto 0));
end Wallace2;

architecture Behavioral of Wallace2 is

signal Cout1,Cout2,Cout3,Cout4,Cout5,Cout6,Cout7,Cout8,Cout9,Cout10,Cout11,Cout12,Cout13,Cout14,Cout15 : std_logic;
signal Cout16,Cout17,Cout18,Cout19,Cout20,Cout21,Cout22,Cout23,Cout24,Cout25,Cout26,Cout27,Cout28 : std_logic;
signal Cout29,Cout30,Cout31,Cout32,Cout33,Cout34,Cout35,Cout36,Cout37,Cout38,Cout39,Cout40,Cout41 : std_logic;
signal Cout42,Cout43,Cout44,Cout45,Cout46,Cout47,Cout48,Cout49,Cout50,Cout51,Cout52,Cout53,Cout54,Cout55 : std_logic;

signal S2,S3,S4,S5,S6,S7,S9,S10,S11,S12,S13,S14 : std_logic;
signal S16,S17,S18,S19,S20,S21,S23,S24,S25,S26,S27,S28 : std_logic;
signal S30,S31,S32,S33,S34,S35,S37,S38,S39,S40,S41,S42 : std_logic;
signal S44,S45,S46,S47,S48,S49 : std_logic;

signal A0B1, A1B1, A2B1, A3B1, A4B1, A5B1, A6B1, A7B1 : std_logic;
signal A0B2, A1B2, A2B2, A3B2, A4B2, A5B2, A6B2, A7B2 : std_logic;
signal A0B3, A1B3, A2B3, A3B3, A4B3, A5B3, A6B3, A7B3 : std_logic;
signal A0B4, A1B4, A2B4, A3B4, A4B4, A5B4, A6B4, A7B4 : std_logic;
signal A0B5, A1B5, A2B5, A3B5, A4B5, A5B5, A6B5, A7B5 : std_logic;
signal A0B6, A1B6, A2B6, A3B6, A4B6, A5B6, A6B6, A7B6 : std_logic;
signal A0B7, A1B7, A2B7, A3B7, A4B7, A5B7, A6B7, A7B7 : std_logic;
signal A1B0, A2B0, A3B0, A4B0, A5B0, A6B0, A7B0 : std_logic;

component fulladder is
    Port ( A : in STD_LOGIC;
           B : in STD_LOGIC;
           Cin : in STD_LOGIC;
           S : out STD_LOGIC;
           Cout : out STD_LOGIC);
end component;

component halfadder is
    Port ( A : in STD_LOGIC;
           B : in STD_LOGIC;
           S : out STD_LOGIC;
           Cout : out STD_LOGIC);
end component;

begin

A1B0 <= A(1) and B(0) ;
A2B0 <= A(2) and B(0) ;
A3B0 <= A(3) and B(0) ;
A4B0 <= A(4) and B(0) ;
A5B0 <= A(5) and B(0) ;
A6B0 <= A(6) and B(0) ;
A7B0 <= A(7) and B(0) ;

A0B1 <= A(0) and B(1) ;
A1B1 <= A(1) and B(1) ;
A2B1 <= A(2) and B(1) ;
A3B1 <= A(3) and B(1) ;
A4B1 <= A(4) and B(1) ;
A5B1 <= A(5) and B(1) ;
A6B1 <= A(6) and B(1) ;
A7B1 <= A(7) and B(1) ;

A0B2 <= A(0) and B(2) ;
A1B2 <= A(1) and B(2) ;
A2B2 <= A(2) and B(2) ;
A3B2 <= A(3) and B(2) ;
A4B2 <= A(4) and B(2) ;
A5B2 <= A(5) and B(2) ;
A6B2 <= A(6) and B(2) ;
A7B2 <= A(7) and B(2) ;

A0B3 <= A(0) and B(3) ;
A1B3 <= A(1) and B(3) ;
A2B3 <= A(2) and B(3) ;
A3B3 <= A(3) and B(3) ;
A4B3 <= A(4) and B(3) ;
A5B3 <= A(5) and B(3) ;
A6B3 <= A(6) and B(3) ;
A7B3 <= A(7) and B(3) ;

A0B4 <= A(0) and B(4) ;
A1B4 <= A(1) and B(4) ;
A2B4 <= A(2) and B(4) ;
A3B4 <= A(3) and B(4) ;
A4B4 <= A(4) and B(4) ;
A5B4 <= A(5) and B(4) ;
A6B4 <= A(6) and B(4) ;
A7B4 <= A(7) and B(4) ;

A0B5 <= A(0) and B(5) ;
A1B5 <= A(1) and B(5) ;
A2B5 <= A(2) and B(5) ;
A3B5 <= A(3) and B(5) ;
A4B5 <= A(4) and B(5) ;
A5B5 <= A(5) and B(5) ;
A6B5 <= A(6) and B(5) ;
A7B5 <= A(7) and B(5) ;
 
A0B6 <= A(0) and B(6) ;
A1B6 <= A(1) and B(6) ;
A2B6 <= A(2) and B(6) ;
A3B6 <= A(3) and B(6) ;
A4B6 <= A(4) and B(6) ;
A5B6 <= A(5) and B(6) ;
A6B6 <= A(6) and B(6) ;
A7B6 <= A(7) and B(6) ;

A0B7 <= A(0) and B(7) ;
A1B7 <= A(1) and B(7) ;
A2B7 <= A(2) and B(7) ;
A3B7 <= A(3) and B(7) ;
A4B7 <= A(4) and B(7) ;
A5B7 <= A(5) and B(7) ;
A6B7 <= A(6) and B(7) ;
A7B7 <= A(7) and B(7) ;

PO : P(0) <= A (0) and B(0);

hall: halfadder port map (A1B0,A0B1,P(1),Cout1);
fa12: fulladder port map (A2B0,A1B1,A0B2,S2,Cout2) ;
fa13: fulladder port map (A2B1,A1B2,A0B3,S3,Cout3) ;
fa14: fulladder port map (A2B2,A1B3,A0B4,S4,Cout4) ;
fa15: fulladder port map (A2B3,A1B4,A0B5,S5,Cout5) ;
fa16: fulladder port map (A2B4,A1B5,A0B6,S6,Cout6) ;
fa17: fulladder port map (A2B5,A1B6,A0B7,S7,Cout7) ;


ha21: halfadder port map (S2,Cout1,P(2),Cout8);
fa22: fulladder port map (A3B0,S3,Cout2,S9,Cout9);
fa23: fulladder port map (A3B1,S4,Cout3,S10,Cout10);
fa24: fulladder port map (A3B2,S5,Cout4,S11,Cout11) ;
fa25: fulladder port map (A3B3,S6,Cout5,S12,Cout12) ;
fa26: fulladder port map (A3B4,S7,Cout6,S13,Cout13) ;
fa27: fulladder port map (A2B6,A1B7,Cout7,S14,Cout14) ;


ha31: halfadder port map (S9,Cout8,P(3),Cout15) ;
fa32: fulladder port map (A4B0,S10,Cout9,S16,Cout16) ;
fa33: fulladder port map (A4B1,S11,Cout10,S17,Cout17) ;
fa34: fulladder port map (A4B2,S12,Cout11,S18,Cout18) ;
fa35: fulladder port map (A4B3,S13,Cout12,S19,Cout19) ;
fa36: fulladder port map (A3B5,S14,Cout13,S20,Cout20) ;
fa37: fulladder port map (A3B6,A2B7,Cout14,S21,Cout21) ; 


ha41: halfadder port map (S16,Cout15,P(4),Cout22) ;
fa42: fulladder port map (A5B0,S17,Cout16,S23,Cout23) ;
fa43: fulladder port map (A5B1,S18,Cout17,S24,Cout24) ;
fa44: fulladder port map (A5B2,S19,Cout18,S25,Cout25) ;
fa45: fulladder port map (A4B4,S20,Cout19,S26,Cout26) ;
fa46: fulladder port map (A4B5,S21,Cout20,S27,Cout27) ;
fa47: fulladder port map (A4B6,A3B7,Cout21,S28,Cout28) ; 


ha51: halfadder port map (S23,Cout22,P(5),Cout29) ;
fa52: fulladder port map (A6B0,S24,Cout23,S30,Cout30) ;
fa53: fulladder port map (A6B1,S25,Cout24,S31,Cout31) ;
fa54: fulladder port map (A5B3,S26,Cout25,S32,Cout32) ;
fa55: fulladder port map (A5B4,S27,Cout26,S33,Cout33) ;
fa56: fulladder port map (A5B5,S28,Cout27,S34,Cout34) ;
fa57: fulladder port map (A5B6,A4B7,Cout28,S35,Cout35) ; 


ha61: halfadder port map (S30,Cout29,P(6),Cout36) ;
fa62: fulladder port map (A7B0,S31,Cout30,S37,Cout37) ;
fa63: fulladder port map (A6B2,S32,Cout31,S38,Cout38) ;
fa64: fulladder port map (A6B3,S33,Cout32,S39,Cout39) ;
fa65: fulladder port map (A6B4,S34,Cout33,S40,Cout40) ;
fa66: fulladder port map (A6B5,S35,Cout34,S41,Cout41) ;
fa67: fulladder port map (A6B6,A5B7,Cout35,S42,Cout42) ; 


ha71: halfadder port map (S37,Cout36,P(7),Cout43) ;
fa72: fulladder port map (A7B1,S38,Cout37,S44,Cout44) ;
fa73: fulladder port map (A7B2,S39,Cout38,S45,Cout45) ;
fa74: fulladder port map (A7B3,S40,Cout39,S46,Cout46) ;
fa75: fulladder port map (A7B4,S41,Cout40,S47,Cout47) ;
fa76: fulladder port map (A7B5,S42,Cout41,S48,Cout48) ;
fa77: fulladder port map (A7B6,A6B7,Cout42,S49,Cout49) ; 


ha81: halfadder port map (S44,Cout43,P(8),Cout50) ;
fa82: fulladder port map (S45,Cout44,Cout50,P(9),Cout51) ;
fa83: fulladder port map (S46,Cout45,Cout51,P(10),Cout52) ;
fa84: fulladder port map (S47,Cout46,Cout52,P(11),Cout53) ;
fa85: fulladder port map (S48,Cout47,Cout53,P(12),Cout54) ;
fa86: fulladder port map (S49,Cout48,Cout54,P(13),Cout55) ;
fa87: fulladder port map (A7B7,Cout49,Cout55,P(14),P(15)) ; 



end Behavioral;