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-- Company: 
-- Engineer: 
-- 
-- Create Date: 14.12.2023 11:19:03
-- Design Name: 
-- Module Name: Brans - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx leaf cells in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity Brauns_Multiplier is

Port ( A : in STD_LOGIC_VECTOR (7 downto 0);

B : in STD_LOGIC_VECTOR (7 downto 0);

P : out STD_LOGIC_VECTOR (15 downto 0));

end Brauns_Multiplier;

architecture Behavioral of Brauns_Multiplier is

component FullAdder

port (A : in STD_LOGIC;

B : in STD_LOGIC;

Cin : in STD_LOGIC;

S : out STD_LOGIC;

Cout : out STD_LOGIC) ;

end component;

component HalfAdder

port (A : in STD_LOGIC;

B : in STD_LOGIC;

S : out STD_LOGIC;

Cout : out STD_LOGIC) ;

end component;

signal A1B0, A2B0, A3B0, A4B0, A5B0, A6B0, A7B0 : std_logic;

signal A0B1, A1B1, A2B1, A3B1, A4B1, A5B1, A6B1, A7B1 : std_logic;

signal A0B2, A1B2, A2B2, A3B2, A4B2, A5B2, A6B2, A7B2 : std_logic;

signal A0B3, A1B3, A2B3, A3B3, A4B3, A5B3, A6B3, A7B3 : std_logic;

signal A0B4, A1B4, A2B4, A3B4, A4B4, A5B4, A6B4, A7B4 : std_logic;

signal A0B5, A1B5, A2B5, A3B5, A4B5, A5B5, A6B5, A7B5 : std_logic;

signal A0B6, A1B6, A2B6, A3B6, A4B6, A5B6, A6B6, A7B6 : std_logic;

signal A0B7, A1B7, A2B7, A3B7, A4B7, A5B7, A6B7, A7B7 : std_logic;

signal C1, C2, C3, C4, C5, C6, C7, C8 : std_logic;

signal C9, C10, C11, C12, C13, C14, C15, C16 : std_logic;

signal C17, C18, C19, C20, C21, C22, C23, C24 : std_logic;

signal C25, C26, C27, C28, C29, C30, C31, C32 : std_logic;

signal C33, C34, C35, C36, C37, C38, C39, C40 : std_logic;

signal C41, C42, C43, C44, C45, C46, C47, C48 : std_logic;

signal C49, C50, C51, C52, C53, C54, C55, C56 : std_logic;

signal S2, S3, S4, S5, S6, S7, S8 : std_logic;

signal S10, S11, S12, S13, S14, S15, S16 : std_logic;

signal S18, S19, S20, S21, S22, S23, S24 : std_logic;

signal S26, S27, S28, S29, S30, S31, S32 : std_logic;

signal S34, S35, S36, S37, S38, S39, S40 : std_logic;

signal S42, S43, S44, S45, S46, S47, S48 : std_logic;

begin

A1B0 <= A (1) and B (0) ;

A2B0 <= A (2) and B (0) ;

A3B0 <= A (3) and B (0) ;

A4B0 <= A (4) and B (0) ;

A5B0 <= A (5) and B (0) ;

A6B0 <= A (6) and B (0) ;

A7B0 <= A (7) and B (0) ;

A0B1 <= A (0) and B (1) ;

A1B1 <= A (1) and B (1) ;

A2B1 <= A (2) and B (1) ;

A3B1 <= A (3) and B (1) ;

A4B1 <= A (4) and B (1) ;

A5B1 <= A (5) and B (1) ;

A6B1 <= A (6) and B (1) ;

A7B1 <= A (7) and B (1) ;

A0B2 <= A (0) and B (2) ;

A1B2 <= A (1) and B (2) ;

A2B2 <= A (2) and B (2) ;

A3B2 <= A (3) and B (2) ;

A4B2 <= A (4) and B (2) ;

A5B2 <= A (5) and B (2) ;

A6B2 <= A (6) and B (2) ;

A7B2 <= A (7) and B (2) ;

A0B3 <= A (0) and B (3) ;

A1B3 <= A (1) and B (3) ;

A2B3 <= A (2) and B (3) ;

A3B3 <= A (3) and B (3) ;

A4B3 <= A (4) and B (3) ;

A5B3 <= A (5) and B (3) ;

A6B3 <= A (6) and B (3) ;

A7B3 <= A (7) and B (3) ;

A0B4 <= A (0) and B (4) ;

A1B4 <= A (1) and B (4) ;

A2B4 <= A (2) and B (4) ;

A3B4 <= A (3) and B (4) ;

A4B4 <= A (4) and B (4) ;

A5B4 <= A (5) and B (4) ;

A6B4 <= A (6) and B (4) ;

A7B4 <= A (7) and B (4) ;

A0B5 <= A (0) and B (5) ;

A1B5 <= A (1) and B (5) ;

A2B5 <= A (2) and B (5) ;

A3B5 <= A (3) and B (5) ;

A4B5 <= A (4) and B (5) ;

A5B5 <= A (5) and B (5) ;

A6B5 <= A (6) and B (5) ;

A7B5 <= A (7) and B (5) ;

A0B6 <= A (0) and B (6) ;

A1B6 <= A (1) and B (6) ;

A2B6 <= A (2) and B (6) ;

A3B6 <= A (3) and B (6) ;

A4B6 <= A (4) and B (6) ;

A5B6 <= A (5) and B (6) ;

A6B6 <= A (6) and B (6) ;

A7B6 <= A (7) and B (6) ;

A0B7 <= A (0) and B (7) ;

A1B7 <= A (1) and B (7) ;

A2B7 <= A (2) and B (7) ;

A3B7 <= A (3) and B (7) ;

A4B7 <= A (4) and B (7) ;

A5B7 <= A (5) and B (7) ;

A6B7 <= A (6) and B (7) ;

A7B7 <= A (7) and B (7) ;

PO : P (0) <= A (0) and B (0) ;

--first stage

P1 : HalfAdder port map (A1B0, A0B1, P (1), C1) ;

S2_1 : FullAdder port map (A2B0, A1B1, C1, S2, C2) ;

P2 : HalfAdder port map (A0B2, S2, P (2), C9) ;

S3_1 : FullAdder port map (A3B0, A2B1, C2, S3, C3) ;

S10_1 : FullAdder port map (A1B2, S3, C9, S10, C10) ;

P3 : HalfAdder port map (A0B3, S10, P (3), C17) ;

S4_1 : FullAdder port map (A4B0, A3B1, C3, S4, C4) ;

S11_1 : FullAdder port map (A2B2, S4, C10, S11, C11) ;

S18_1 : FullAdder port map (A1B3, S11, C17, S18, C18) ;

P4 : HalfAdder port map (A0B4, S18, P (4), C25) ;

S5_1 : FullAdder port map (A5B0, A4B1, C4, S5, C5) ;

S12_1 : FullAdder port map (A3B2, S5, C11, S12, C12) ;

S19_1 : FullAdder port map (A2B3, S12, C18, S19, C19) ;

S26_1 : FullAdder port map (A1B4, S19, C25, S26, C26) ;

P5 : HalfAdder port map (A0B5, S26, P (5), C33) ;

S6_1 : FullAdder port map (A6B0, A5B1, C5, S6, C6) ;

S13_1 : FullAdder port map (A4B2, S6, C12, S13, C13) ;

S20_1 : FullAdder port map (A3B3, S13, C19, S20, C20) ;

S27_1 : FullAdder port map (A2B4, S20, C26, S27, C27) ;

S34_1 : FullAdder port map (A1B5, S27, C33, S34, C34) ;

P6 : HalfAdder port map (A0B6, S34, P (6), C41) ;

S7_1 : FullAdder port map (A7B0, A6B1, C6, S7, C7) ;

S14_1 : FullAdder port map (A5B2, S7, C13, S14, C14) ;

S21_1 : FullAdder port map (A4B3, S14, C20, S21, C21) ;

S28_1 : FullAdder port map (A3B4, S21, C27, S28, C28) ;

S35_1 : FullAdder port map (A2B5, S28, C34, S35, C35) ;

S42_1 : FullAdder port map (A1B6, S35, C41, S42, C42) ;

P7 : HalfAdder port map (A0B7, S42, P (7), C49) ;

S8_1 : HalfAdder port map (A7B1, C7, S8, C8) ;

S15_1 : FullAdder port map (A6B2, S8, C14, S15, C15) ;

S22_1 : FullAdder port map (A5B3, S15, C21, S22, C22) ;

S29_1 : FullAdder port map (A4B4, S22, C28, S29, C29) ;

S36_1 : FullAdder port map (A3B5, S29, C35, S36, C36) ;

S43_1 : FullAdder port map (A2B6, S36, C42, S43, C43) ;

P8 : FullAdder port map (A1B7, S43, C49, P(8), C50) ;

S16_1 : FullAdder port map (A7B2, C8, C15, S16, C16) ;

S23_1 : FullAdder port map (A6B3, S16, C22, S23, C23) ;

S30_1 : FullAdder port map (A5B4, S23, C29, S30, C30) ;

S37_1 : FullAdder port map (A4B5, S30, C36, S37, C37) ;

S44_1 : FullAdder port map (A3B6, S37, C43, S44, C44) ;

P9 : FullAdder port map (A2B7, S44, C50, P(9), C51) ;

S24_1 : FullAdder port map (A7B3, C16, C23, S24, C24) ;

S31_1 : FullAdder port map (A6B4, S24, C30, S31, C31) ;

S38_1 : FullAdder port map (A5B5, S31, C37, S38, C38) ;

S45_1 : FullAdder port map (A4B6, S38, C44, S45, C45) ;

P10: FullAdder port map (A3B7, S45, C51, P(10), C52) ;

S32_1 : FullAdder port map (A7B4, C24, C31, S32, C32) ;

S39_1 : FullAdder port map (A6B5, S32, C38, S39, C39) ;

S46_1 : FullAdder port map (A5B6, S39, C45, S46, C46) ;

P11: FullAdder port map (A4B7, S46, C52, P(11), C53) ;

S40_1 : FullAdder port map (A7B5, C32, C39, S40, C40) ;

S47_1 : FullAdder port map (A6B6, S40, C46, S47, C47) ;

P12: FullAdder port map (A5B7, S47, C53, P(12), C54) ;

S48_1 : FullAdder port map (A7B6, C40, C47, S48, C48) ;

P13: FullAdder port map (A6B7, S48, C54, P(13), C55) ;

P14: FullAdder port map (A7B7, C48, C55, P(14), C56) ;

P15: P(15) <= C56 ;

end Behavioral;