library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity wallace is
    Port ( A : in  STD_LOGIC_VECTOR (3 downto 0);
           B : in  STD_LOGIC_VECTOR (3 downto 0);
           P : out  STD_LOGIC_VECTOR (7 downto 0));
end wallace;
 
architecture Behavioral of wallace is
 
component Fulladder is
    Port ( A : in  STD_LOGIC;
           B : in  STD_LOGIC;
         Cin : in  STD_LOGIC;
         Sum : out  STD_LOGIC;
       Cout : out  STD_LOGIC);
end component;
 
component Halfadder is
    Port ( A : in  STD_LOGIC;
           B : in  STD_LOGIC;
         Sum : out  STD_LOGIC;
        Cout : out  STD_LOGIC);
end component;
 
 
signal S2,S3,S4,S6,S7,S8: std_logic;
signal C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11: std_logic;
 
signal A1B0 : std_logic;
signal A2B0 : std_logic;
signal A3B0 : std_logic;
 
signal A0B1 : std_logic;
signal A1B1 : std_logic;
signal A2B1 : std_logic;
signal A3B1 : std_logic;
 
signal A0B2 : std_logic;
signal A1B2 : std_logic;
signal A2B2 : std_logic;
signal A3B2 : std_logic;
 
 
signal A0B3 : std_logic;
signal A1B3 : std_logic;
signal A2B3 : std_logic;
signal A3B3 : std_logic;
 
 
 
begin
 
 
A1B0 <= A(1)and B(0);
A2B0 <= A(2)and B(0);
A3B0 <= A(3)and B(0);
A0B1 <= A(0)and B(1);
A1B1 <= A(1)and B(1);
A2B1 <= A(2)and B(1);
A3B1 <= A(3)and B(1);
A0B2 <= A(0)and B(2);
A1B2 <= A(1)and B(2);
A2B2 <= A(2)and B(2);
A3B2 <= A(3)and B(2);
A0B3 <= A(0)and B(3);
A1B3 <= A(1)and B(3);
A2B3 <= A(2)and B(3);
A3B3 <= A(3)and B(3);
 
 
--first stage
 
P0          : P(0) <= A(0) and B(0) ;
 
ha11 : Halfadder port map(A=>A1B0,B=>A0B1,S=>P(1),Cout=>C1);
fa12 : Fulladder port map(A=>A2B0,B=>A1B1,Cin=>A0B2,S=>S2,Cout=>C2);
fa13 : Fulladder port map(A=>A3B0,B=>A2B1,Cin=>A1B2,S=>S3,Cout=>C3);
ha14 : Halfadder port map(A=>A3B1,B=>A2B2,S=>S4,Cout=>C4);
 
 
--second stage
ha21 : Halfadder port map(A=>S2,B=>C1,S=>P(2),Cout=>C5);
fa22 : Fulladder port map(A=>S3,B=>C2,Cin=>A0B3,S=>S6,Cout=>C6);
fa23 : Fulladder port map(A=>S4,B=>C3,Cin=>A1B3,S=>S7,Cout=>C7);
fa24 : Fulladder port map(A=>A3B2,B=>C4,Cin=>A2B3,S=>S8,Cout=>C8);
 
 
 
--third stage
ha31 : Halfadder port map(A=>S6,B=>C5,S=>P(3),Cout=>C9);
ha32 : Fulladder port map(A=>S7,B=>C6,Cin=>C9,S=>P(4),Cout=>C10);
ha33 : Fulladder port map(A=>S8,B=>C7,Cin=>C10,S=>P(5),Cout=>C11);
ha34 : Fulladder port map(A=>A3B3,B=>C8,Cin=>C11,S=>P(6),Cout=>P(7));
 
 
end Behavioral;