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-- Company: 
-- Engineer: 
-- 
-- Create Date:    20:55:38 03/31/2014 
-- Design Name: 
-- Module Name:    fsm_t1 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity state_machine is
    Port ( Clk : in  STD_LOGIC;
           Rset : in  STD_LOGIC;
           W : in  STD_LOGIC;
           X : out STD_LOGIC;
			  sa: out std_logic;
			  sb: out std_logic;
			  sc: out std_logic;
			  sd: out std_logic;
			  se: out std_logic
			 );
			  
end entity state_machine;

architecture Behavioral of state_machine is


type state_type is (state_a, state_b, state_c, state_d, state_e);
signal present_state: state_type;
signal next_state : state_type;

begin

state:process (present_state, Rset,W)

	begin
		if Rset='1' then 
			next_state <= state_a;
			X <= '0';
		else if Rset='0' then 
				if W='0' Then    
					case present_state is
						when state_a => 	next_state <= state_a; X <= '0';
						when state_b => 	next_state <= state_c; X <= '0';
						when state_c => 	next_state <= state_a; X <= '0';
						when state_d => 	next_state <= state_a; X <= '0';
						when state_e => 	next_state <= state_e; X <= '1';
						when others => NULL;
					end case;
				else if W='1' then 
						case present_state is
							when state_a => 	next_state <= state_b; X <= '0';
							when state_b => 	next_state <= state_b; X <= '0';
							when state_c => 	next_state <= state_d; X <= '0';
							when state_d => 	next_state <= state_e; X <= '1';
							when state_e => 	next_state <= state_e; X <= '1';
							when others => NULL;
						end case;
					  end if; 
				 end if;  
			   end if; 
		 end if; 
		 
		 if (present_state=state_a) then	sa <='1'; else sa<='0'; end if;
		 if (present_state=state_b) then	sb <='1'; else sb<='0'; end if;
		 if (present_state=state_c) then	sc <='1'; else sc<='0'; end if;
		 if (present_state=state_d) then	sd <='1'; else sd<='0'; end if;
		 if (present_state=state_e) then	se <='1'; else se<='0'; end if;		 

		 
end process state;
	
clock: process(Clk)
	begin
		if((Clk='1') and (Clk'last_Value='0')) Then
			present_state <= next_state;
		end if;
end process clock;	
	
end Behavioral;